The DINAR1_HDMI_ETH_USB is a daughter card that adds HDMI receive and transmit interfaces to the DINI Group line of FPGA-based ASIC prototyping products. This card can be used standalone. Standalone operation requires loopback board on the DINAR1 connector (provided) and a separate ATX power supply.
1. HDMI - Receive and Transmit
The DINAR1_HDMI_ETH_USB has two HDMI receive channels and a single HDMI transmit channel. The Analog Devices ADV7511 is used for the transmit channel. This transmitter features full version 1.4 compliance including Audio return channel (ARC) and 3D video support. All features of the chip are available including DVI. A list of the functionality contained in the ADV7511 is best gotten from the datasheet here: ADV7511 Datasheet.
The Analog Devices ADV7612 is used for the receive channels. This chip supports dual HDMI channels and is fully v1.4a compliant. As with the ADV7612, it is best to get the full list of functionality from the datasheet: ADV7612 Datasheet.
2. The FPGA - Xilinx Kintex-7
We use a single FPGA from the Xilinx Kintex-7 in the FFG676 package, primarily for voltage translation. This package has 400 I/O with the majority utilized.
Three possible FPGAs can be stuffed: 7K410T, 7K325T, and 7K160T. All three FPGAs come in a variety of speed grades (-1,-2/2L, -3) with -3 being the fastest. All speed grades are applicable to this application. Table 1 depicts the resources of the FPGAs with the extreme Xilinx marketing exaggerations remorselessly severed. These are large but low-cost FPGAs. The 7K410T is capable of handling ~3M ASIC gates of logic, with the 7K325T capable of ~2.3 million gates. Features of the Kintex-7 FPGAs include efficient, dual-register 6-input look-up table (LUT) logic, 18 Kb (2 x 9 Kb) block RAMs, and second generation DSP48E1 slices (includes 25 x 18 multipliers). Floating point functions can be implemented using these DSP slices. 100% of the FPGA resources are available for your use. This FPGA is vast overkill for voltage translation.
3. DDR3 DRAM - A large amount of local, bulk memory
A single PC3-10600 DDR3 memory in a 256M x 16 configuration is provided on a high performance I/O bank. This DDR3 memory is intended for HDMI frame buffering, but can be used for any purpose. The Xilinx Memory Interface Generator (MIG) is used to provide the memory controller. As always, we supply examples and reference designs to help you with all of your memory interface issues. Please check with us to make sure that what we ship for no charge meets your requirements.
4. Miscellaneous Peripherals
Dual RS232 ports, a 1000-baseT Ethernet Phy, and a USB3.0 interface are provided. Also, a standard ARM JTAG 20 interface connector enables ARM debug if you put one of those processors in the FPGA.
5. DINAR1 Connector
The DINAR1_HDMI_ETH_USB uses a connector standard called DINIARRAY (DINAR1), which utilizes 320-pin Samtec SEAM series connectors. This board is intended to mate to any DINI Group ASIC Prototyping card with a DINAR1 interface. Where applicable, the signals are routed differentially and can run at the limit of the Virtex-7/Kintex-7 FPGA I/Os: 710 MHz (assumes -2 or faster).
6. Status LEDs, Debug
As with all of our ASIC emulation boards, the DINAR1_HDMI_ETH_USB is loaded with LEDs. The LEDs can be used to test mood lighting around your HDMI monitor. When testing this make sure an adult is present and don’t fall asleep. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition the somnolence enhancement. A JTAG connector provides an interface to ChipScope and other third party debug tools.
l DINAR1 daughter card
Ø Standalone operation supported with external power supply and loopback card
l Dual HDMI receiver channels (v1.4a) using ADV7612
Ø HDTV formats up to 1080p 36-bit Deep Color
Ø Display resolutions up to UXGA (1600 x 1200 at 60 Hz)
l Single HDMI output (v1.4) using ADV7511
Ø DVI 1.0-compatible transmitter
Ø All HDTV formats including 1080p with 12-bit Deep Color
Ø Audio return channel (ARC)
Ø 3D video.
l Xilinx Kintex-7 FPGA (FFG676), primary for voltage translation:
Ø 7K410T-3,-2,-1, 7K325T-3,-2,-1, 7K160T-3,-2,-1(fastest to slowest)
l ~3 million ASIC gates (ASIC measure) when stuffed with 7K410T
l 254k flip-flop/6-input LUTs (708k total FFs)
l 3.578 Kbytes total FPGA block memory (1590, 18-kbit blocks)
l 1540, 25x18 multipliers
l 256Mb x 16 DDR3 memory for frame buffer storage
l ARM JTAG 20 debug connector
Ø +3.3V I/O tolerant
l 1000-baseT Ethernet Phy
l Dual Serial ATA (SATA II)
l Dual RS232 ports for embedded FPGA-based SOC uP debug (two channels)
l Full support for embedded logic analyzers via JTAG interface
l Status FPGA-controlled LEDs
l Enough multicolored LEDs for effective mood lighting.