The DNV7F4A is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DNV7F4A is a stand-alone system and can be hosted by 4-lane PCIe cable (GEN2), USB or Ethernet. A single DNV7F4A configured with four Virtex-7, 7V2000Ts can emulate up to 56 million gates of logic as measured by a reasonable ASIC gate counting standard. Two DNV7F4A can be linked together, doubling this gate count to 112 million seamlessly. More DNV7F4As can be linked together if the design grows larger. The gate count estimate number does not include embedded memories and multipliers resident in the FPGA fabric. One hundred percent (100%) of the Virtex-7 FPGA resources are available to the user application. The DNV7F4A achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx's 28nm Virtex-7 family.
1. Stacking two or more boards together
Two or more DNV7F4A can be linked together to increase n-times the resources. This page here has more detail: 'Stacking DNV7F4A boards together'. All functionality is seamlessly maintained including the high performance data movement via the NMB busses. When two DNV7F4A stuffed with the 7V2000T are stacked, the resulting system can handle at least 112 million ASIC gates. When more than two DNV7F4A with 7V2000T are linked, the gate number grows correspondingly. Call in if you need to link a large number of DNV7F4A because some additional hardware might be rquired.
2. Virtex-7 FPGA from Xilinx
The DNV7F4A uses a high I/O-count, 1925-pin flip-chip BGA package. In this package, the 7V2000T has 1200 I/Os and 16 GTX channels. All are utilized. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGAs. All FPGA to FPGA interconnect is routed as LVDS, but can be used single-ended at a reduced frequency. 100% of the resources of the four Virtex-7 FPGA are dedicated to the user application.
Introducing the Xilinx Virtex-7 7V2000T. When stuffed with four of these devices, DNV7F4A is capable of prototyping >56 million gates of ASIC logic with plenty of resource margin. This is a ground breaking device and the first to utilize 2.5 silicon dimensions. Prior to the stacked 7V2000T, the biggest challenge in FPGA-based ASIC prototyping was logic partitioning. This difficult task is nearly eliminated with this large quad-slice device.
3. The Marvell MV78200 Discovery™ Dual CPU
A MONSTER for data movement and manipulation
Easy FPGA configuration is a required feature of large FPGA boards. We use an onboard CPU to handle this function. We choose a Marvell MV78200 from the Discovery™ Innovation CPU family. Bluntly stated, this CPU is massive, massive overkill for the mundane task of FPGA configuration. The MV78200 comes a variety high performance interfaces, and all can be utilized to your advantage.
4. Dual Sheeva™ CPUs, 1GHz with floating point
First and foremost are dual CPUs. And after we are done configuring the FPGAs we dedicate both CPUs to your application. The CPUs in the MV78200 are Marvell Sheeva™ cores, which are ARM v5TE compliant. The CPUs are clocked at 1GHz and each processor has a single and double precision floating point unit. A fixed 1 GB, DDR2 memory is standard and is useful for large amounts of high speed data buffering. The memory is organized as 128M x 64 and clocked at the full frequency allowed: 400MHz (800MHz effective with DDR). This DDR2 bank is shared between the two CPUs. Boot code is resident in an SPI Flash, and application code is downloaded via any port: PCIe, USB, and Ethernet. We ship Linux as the standard operating system. Options exist for VxWorks and other real-time operating systems. Contact the factory for more information.
5. PCI Express
The Marvell 78200 acts as a two-port high-speed PCI Express switch (2.5 Gb/s). It connects the user FPGA at 4-lane PCI Express speeds to a host computer. The Marvell 78200 has multiple DMA engines to pump data to and from any port. The user interface on the FPGA is a simple-to-use, pipelined A/D bus running at 6.4Gb/s. Drivers for data movement to and from a host machine are provided. A simple example FPGA design and host computer application streaming data at PCI Express x4 bandwidth to the user FPGA is provided.
6. Two Serial-ATA Ports (SATA II)
The MV78200 has two Serial-ATA Generation 2 (SATA II) ports, each capable of running at 3.0 Gb/s. SATA is intended for high speed data transfer to/from serial-ATA hard drives. Two SATA connectors are provided, allowing for direct, high-speed interfacing to external hard drives. The MV78200 has specialized enhanced DMA(EDMA) engines for HDD data transfer with 512-byte buffer for each channel. Examples of all possible data movement options, with source, are included.
7. GbE - 802.3 Gigabit Ethernet
The MV78200 can be controlled over its built-in Ethernet port. The interface is a standard RJ45 connector. This port can be used to configure FPGAs, set board clocks and other resources, and access the Linux terminal. This terminal can also be used to send data to and from the user FPGA design at gigabit Ethernet speeds.
8. Expansion connectors for customization, memory, and stacking
The DNV7F4A uses a connector standard called DINIARRAY (DINAR1), which utilizes 320-pin Samtec SEAM series connectors. Two of these connectors are attached to each field FPGA, enabling expansion, customization, and stacking. This is a non-proprietary, industry standard connector and the mating connector is readily available. We can provide the mating connector to you at our cost. We are not fans of proprietary, hard-to-get, outrageously priced expansion connectors. The 150 signals (72 pairs) to/from each of these expansion connectors are routed differentially and can run at the limit of the Virtex-7 FPGA I/Os: 700 MHz (assumes -2 or faster). Clocks, resets, and presence detection, along with abundant (fused) power are included in each connector.
Memory can be added to the DNV7F4A via the DINAR1 expansion connector using the DINAR1_SODM204 expansion card. Each DINAR1 can host a single DINAR1_SODM204 expansion card, so as many as four of these cards can be used DNV7F4A. The DINAR1_SODM204 has a single 204-pin SODIMM socket. Off-the-shelf DDR3 SODIMM modules work fine, allowing you to add up to 8GB of low cost memory in each DINAR1 position. In addition, we have compatible SODIMMs in the following variations: flash, SSRAM, QDR II+, mobile SDRAM, mictors, USB2.0 PHYs, and more.
10. Easy Configuration via PCIe, USB, or Ethernet
Configuration of the FPGAs is under the control of the Marvell CPU. Configuration data can be provided over PCI Express, USB, Ethernet, or on-board non-volatile memory. It can be copied to the board using a USB memory stick (provided). Configuration occurs automatically after the CPU boots. Sanity checks are performed automatically on the configuration files, streamlining the configuration process in the case of human error. Multiple LEDs provide instant status and operational feedback.
11. Status LEDs, Debug
As with all of our ASIC emulation boards, the DNV7F4A is loaded with LEDs. The LEDs are stuffed in several different colors (red, green, blue, orange et al.).There are enough LEDs here to blind a hamster. So please, get sunglasses for those laboratory hamsters. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to the party enhancing. A JTAG connector provides an interface to ChipScope and other third party debug tools.
l Hosted via
Ø 4-lane GEN2 PCIe via iPASS cable,
Ø 10/100/1000BASE-T Ethernet or
l Four Xilinx Virtex-7 FPGAs (FLG1925):
Ø 7V2000T-2,-1 (fastest to slowest)
l 56+ million ASIC gates (ASIC measure) when stuffed with four 7V2000Ts
l Memory can be added using DINAR1_SODM204 on any (or all) DINAR1 expansion connector(s):
Ø Off-the-shelf DDR3 DRAM SODIMM204 modules
Ø DNSODM204_SE (mobile SDRAM)
Ø DNSODM204_USB (USB2.0 PHY)
Ø DNSODM204_QUADMIC (four Mictor connectors)
Ø DNSODM204_MICTOR_IO (Mictor,IDC,DIP switch,etc)
l FPGA to FPGA bidirectional data movement with dedicated single GTX channel
Ø Mesh configuration
l A↔B, A↔C, A↔D, B↔C, B↔D,C↔D
Ø Characterized to 10 Gb/s with assuming -2 and 6 Gb/s with -1.
l High Speed interfaces (-2 speed grade required for 10 GbE):
Ø FPGA A
l QSFP+ module for 4x 10 GbE or single 40 GbE
l Serial ATA (SATA II), host
Ø FPGA B
l QSFP+ module for 4x 10 GbE or single 40 GbE
l Serial ATA (SATA II), device
Ø FPGA C:
l 4x SFP+ modules for 10 GbE
l Single channel SMAs
Ø FPGA D
l 4-lane iPASS connector for PCIe (GEN1/GEN2)
l Single channel SMAs
l Dual SEARAY GTP Expansion headers, 8-lanes each. One per FPGA. Each capable of supporting:
Ø 8-lane PCIe (GEN1/GEN2) Consult factory for GEN3
Ø 2x CX4 - Ethernet, XAUI, Infiniband
Ø 8x SFP+ modules for 10 GbE
Ø 2x QSFP+ modules for 40 GbE
Ø 8x USB3.0/2.0 (A,AB,B)
Ø 8x Serial ATA II (SATA II)
Ø 8x SMA
l NMB busses - Preconfigured high speed data movement between field FPGAs and Config FPGA
Ø 400 MB/s DMA between FPGAs and Config FPGA
l A↔B, A↔C, A↔D, B↔C, B↔D,C↔D
l FPGA[A,B,C,D] ↔ Config FPGA (Marvell uP)
l YMB Bus for seamless stacking
l Marvell MV78200 Discovery Innovation Dual CPU
Ø 1 GHz clock
Ø Dual USB2.0 ports (Type B connector)
Ø Dual Serial-ATA II connectors for 2 external hard drives (SATA II)
Ø Gigabit Ethernet interface
l 10/100/1000 GbE (RJ45 connector)
Ø SheevaTM CPU Core (ARM v5TE compliant)
l Out-of-order execution
l Single and double-precision IEEE compliant floating point
l DSP instructions boosts performance for signal processing applications
l MMU to support virtual memory features
l Dual Cache: 32 KB for data and instruction, parity protected
l L2 cache: 512 KB unified L2 cache per CPU (total of 1MB), ECC protected.
Ø 1 GB external DDR2 SDRAM
l Organized in a 128M x 64 configuration
l 400 MHz (800 MHz data rate with DDR)
Ø RS232 port for terminal-style observation
Ø After configuration, both CPUs dedicated entirely to user application
Ø Linux operating system
l Source and examples provided via GPL license (no charge)
l ~15 seconds to CPU boot
l Five independent low-skew global clock networks and single fixed clock
Ø Five, high-resolution, user-programmable synthesizers for G0-G4
l Silicon Labs Si5326: 2kHz to 945 MHz
Ø User-configurable via Marvell uP RS232, USB, PCIe, or Ethernet
Ø Global clock networks differentially distributed and balanced
l Flexible customization via 2 daughter card positions per FPGA
Ø DINAR1 expansion connector
l Connector is non-proprietary, readily available, and cheap
Ø 72 LVDS pairs + clocks (or 150 single-ended)
Ø 700 MHz on all signals with source synchronous LVDS
Ø Signal voltage set by daughter card (+1.2V to +1.8V)
Ø Supplied power rails (fused):
l +12V (24W max)
l +3.3V (10W max)
Ø Pin multiplexing to/from daughter cards using LVDS (up to 10x)
Ø Support FMC, logic analyzer, memory expansion
l Fast and Painless FPGA configuration
Ø USB, cabled PCIe, Ethernet, JTAG
Ø Stand-alone configuration with USB stick
Ø Configuration Error reporting
Ø Accelerated configuration readback for advanced debug
l RS232 port for embedded FPGA-based SOC uP debug
Ø Accessible from all FPGAs via separate 2-signal bus
l Full support for embedded logic analyzers via JTAG interface
l Noninvasive debug via FPGA register readback: DN_Readbacker
l FPGA-controlled Status LEDs
Ø Enough multicolored LEDs to blind a hamster.
l PLEASE NOTE:
Ø SEAM_D CANNOT be used with standard width DNSEAM daughter cards.
Ø It requires a narrow form-factor DNSEAM board. Please contact the factory if you need to use SEAM_D.