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Pin Multiplexing

Pin Multiplexing

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2018-07-04 浏览次数: 86
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The Dini Group LVDS IO Pin Multiplexing design (DNLVDS_PINMUX) is intended to ease the strain of prototyping an ASIC design that spans multiple FPGAs by providing a low-latency IO pin multiplexing design. A latency of one clock cycle is achievable end-to-end, so the multiplexing essentially becomes invisible to the ASIC design. IO rates are maximized to allow for the highest internal frequency possible. Eye detection training and real-time eye monitoring are implemented inside the receiver module.

Features Summary

Up to 100:1 multiplexing per LVDS pair

l   IO speeds of up to 1.3Gbps per LVDS pair

l   Zero clock cycles of added latency on internal clock

l   Low FPGA resource requirements

l   Built-in link training, real-time eye monitoring, tap adjustment, and error detection


HDL Module Interface

TX Module

Data of width MULTIPLEX_FACTOR on the internal domain is muxed on the clk_oserdes domain to a width of OSERDES_WIDTH, combined with start symbols and generated checksum data, and then sent to the OSERDES module. It is then muxed into serial data and transmitted across the physical interface as source-synchronous LVDS data.



RX Module 

The ISERDES primitive receives the source-synchronous LVDS data and clock and outputs a word of width ISERDES_WIDTH. This word is then further de-muxed into the full word width of MULTIPLEX_FACTOR and output with a data valid indicator. The received checksum is verified against a generated data checksum.


Link Training 
After reset, the link training state machine will expect a training pattern to be transmitted to the ISERDES, and will use bitslip and IDELAY calibration to find the center of the data window. When the link training state machine has finished calibration, it will assert the training_locked signal. The TX module will continue to transmit training data for some period after training_locked has been asserted; the data_valid signal will be asserted at the start of valid user data.

Error Detection (Checksum) 
A checksum of width ISERDES_WIDTH is generated by XOR-ing each valid data word out of the ISERDES module. An identical generator resides in the TX module, and the checksum will be sent after the last valid data word from the TX to the RX module. The generated and received checksums will be compared, and transmission_error_detected will signal a difference in checksums. The signal transmission_error_detected is not latched; it will assert for one clock cycle for each error detected.

Real-time Eye Monitoring 
After initial link training is complete, a slave ISERDES module will be used to detect shifts in the valid data window that can occur due to voltage or temperature changes as specified by Xilinx App Note XAPP860
 () . This monitor will only be included for values of ISERDES_WIDTH of 6 or less; if the slave ISERDES is required for actual data transfer, it cannot be dedicated to eye monitoring.

Bus/Bank Requirements 
A maximum of 19 LVDS pairs are available to use per module. This limit arises because no more than a single bank of pins is allowed to be connected to the RX module. All DATA_P/N pins for a given module must be sourced from a single bank, and that bank must also contain CLK_P/N for clocking structure purposes. The CLK_P/N must be received on a clock-capable pin.

Performance 
The physical limitations listed here result from the capabilities of the FPGA technology and circuit boards used, and are not inherent in the design. Some capabilities listed here are only available on higher speed-grade parts.

IO Transmission Rates 
IO rates are defined in the Performance Characteristics section in the following data sheets.
For Virtex 5, from DS202: 

Note that the maximum IO rate is determined not only by the FPGA capability by also by the characteristics of the circuit board. Verify that the busses intended for use are capable of high data-rate transfer by contacting the circuit board provider. Also note that for some speed grades, the transmit frequency and receive frequency do not match, limiting the maximum performance to the lower of the two numbers.

Dini Group Advantage 
There are many board design flaws that can degrade the performance of FPGA interconnect. Extra vias, connectors, cables and long trace lengths may contribute to transmission errors at high IO rates. Additionally, high-jitter clock sources also limit performance.

All Dini Group boards have been designed to maximize the speed of the FPGA interconnect busses, and are intended to run at the maximum ability of the FPGAs. All interconnect busses have the minimum number of vias, do not rely on cables or connectors and are laid out to avoid crosstalk with other lines. Dini Group boards use the highest precision clock synthesizers available. The emphasis on performance evident in the DNLVDS_PINMUX modules is reflected in the Dini Group circuit boards.

Multiplex and Clock Settings 
Equations for use (and to be explained) in the following section: 

l  IO_rate = Internal_frequency * Clock_ratio * OSERDES_WIDTH

l  Clock_ratio = 7 + (MULTIPLEX_FACTOR/OSERDES_WIDTH)

l  Clock_ratio = clk_oserdes_frequency / clk_core_frequency

A MMCM (or PLL if using Virtex5 technology) must be used to generate the clocks for the TX module (clk_coreclk_oserdes, and clk_oserdes_2x) in order to guarantee phase alignment. This restricts the input to the MMCM (PLL) to a minimum frequency of 10 (19) MHz; with a minimum internal operating frequency, there is a maximum amount of multiplexing that can occur while still respecting the maximum IO rate.

The ratio between clk_core and clk_oserdes depends on the amount of multiplexing done. All of the latency on the fast (clk_oserdes) domain required for physical data transfer must be accommodated (and encompassed) by the slow (clk_core) domain. The OSERDES and ISERDES modules each require 2 clock cycles of latency. There will be 1 clock cycle of latency per multiplexed word for the mux in the TX module, and 1 clock cycle of resync in the RX module. Assume a maximum of 1ns of board delay, and .5ns each for clk-to-out and setup/hold in the OSERDES and ISERDES modules. This gives us a total of 2+2+N+1 clock cycles + 2 ns of latency, where N is the mux factor (MULTIPLEX_FACTOR/OSERDES_WIDTH). For example, for 20:1 multiplexing using an O/ISERDES_WIDTH of 4, we would get 2+2+(20/4)+1 = 10 clock cycles + 2ns of latency; if our IO rate were 1Gbps, then this would mean that our clock ratio would need to be (10*1ns + 2ns) / (1ns/clock) = 12.

Figure 5 - Clock and Data Timing Diagram

The figure shows an IOSERDES_WIDTH of 4, a clock ratio of 12, and 20:1 multiplexing. Latencies for the first word of OSERDES/ISERDES data and the entire multiplexed data are marked with red arrows. Notice that a start symbol is sent before each multiplexed word, and a checksum is sent after. There is no penalty for selecting a higher-than-needed clock ratio other than a reduced internal operating frequency. If a lower-than-needed clock ratio is supplied, data will not transfer properly and could additionally be subject to setup timing errors.

The upper bound of the internal frequency is determined by the IO rate, OSERDES_WIDTH, and the clock ratio. For example, a clock ratio of 12 and an IO rate of 1Gbps w/ an OSERDES_WIDTH of 4 would limit clk_core to a maximum frequency of (1 GHz/ (12*4)) = 20.83MHz.


IP for LVDS Pin Multiplexing

l    Up to 100:1 multiplexing per LVDS pair

l    IO speeds of up to 1.3 Gbps per LVDS pair

l    Zero clock cycles of added latency on internal clock

l    Low FPGA resource requirements

l    Built-in link training, real-time eye monitoring, tap adjustment, and error detection

l    Dini Group Boards Supported:

Ø Xilinx Virtex-Ultrascale:

l  DNVUF4A

l  DNVUF2A

l  DNVUF1A

l  DNVUF2_HPC_PCIe

Ø    Xilinx Virtex-7:

l  DNV7F4A

l  DNV7F2B

l  DNV7F2A

l  DNV7F1A

Ø    Xilinx Virtex-6:

l  DN-DualV6-PCIe-4

l  DNV6_F2PCIe

l  DNV6F6PCIe

l  DN2076k10

Ø    Xilinx Virtex-5:

l  DN9000K10PCIe-8T

l  DN9200K10PCIe-8T

l  DN9002K10PCIe-8T


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