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TOE_IoT

TOE_IoT

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2018-07-05 浏览次数: 285
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TCP Offload Engine IoT (TOE_IoT) is FPGA-based IP that receives and transmits Ethernet/IP/TCP packets on Ethernet networks. TOE_IoT delivers payload data, in order, to the user.s application with:

Extra TCP/IP packet fields removed

l    No missing data

l    Verified by appropriate CRCs and checksums

l    Flow control

The purpose is to offload the TCP/IP function from the embedded CPU and perform it directly in FPGA-based hardware. This IP is specifically optimized for embedded, IoT applications where high data bandwidth and/or guaranteed latency is required. TOE_IoT does this by eliminating the need for host processor intervention when analyzing data packets. This IP is designed to be utilized in FPGA-based embedded, IoT-type appliances where guaranteed latency and/or high bandwidth data movement in a standard network is required. When configured with appropriate networking HW, the TOE_IoT can achieve 90% loading with guaranteed latency.


The TOE_IoT works at the full 10GbE line rate and was developed internally at DINI Group. Consult the factory for 40 GbE and 100 GbE performance specifications. TCP Offload is useful in embedded system where the data throughput requirements exceed the embedded processor.s ability to service. Data critical functions are moved and executed directly in the FPGA. Infrequent, non-data TCP/IP functions such as setup/teardown, ARP, ping, DHCP, et al) are passed through to the (required) embedded CPU. At the intended target frequency of 156.25 MHz, the TOE_IoT operates at the full 10GbE line rate, generating no Ethernet pause frames.

FPGA Resource Utilization (click to enlarge)


l FPGA TCP Offload Engine optimized for IoT and related embedded networking applications

Ø Guaranteed latency

Ø    High data bandwidth

l    128 TCP/IP sessions per instantiated TOE_IoT

Ø    Additional TOE_IoTs can be cascaded to support multiple sessions

l  Number of sessions is limited only by FPGA and external memory resources

l    Supplied as Verilog source

l    Integrated CPU bridge (required)

Ø    AXI, PCIe et al.

l    Simulation models and text fixtures

l    CPU NOT involved in payload data transfer

Ø    0% CPU load during middle of TCP session

Ø    TCP data packets handled by TOE_IoT not passed to CPU

l    Full 10GbE line rate

Ø    No Ethernet pause frames generated

Ø    Consult factory for 40/100 GbE

Ø    Fully compatible with 1 GbE and slower networks

l    CPU required, but only for high complexity/low importance network features:

Ø    setup/teardown of TCP session

Ø    ARP, ping, DHCP, SMTP, et. al.

Ø    C source supplied for these functions

l  Compiles to any known embedded processor

l  FPGA:

l  Intel/Altera Nios, Nios II

l  Xilinx Zynq, MicroBlaze

l  Processor:

l  ARM, MIPS

l  Windows 10 IoT

l  Embedded Linux

l    Layers 2, 3, 4, 5 (datalink, network, transport, and session)

l    Layers 6, 7 (presentation , application) is user.s responsibility in FPGA

l    MTU of 1536 bytes

l    CRC validation and checksum validation

Ø    Ethernet CRC validation

Ø    IP and TCP checksum validation

l    Reordering of out-of-order packets

l    Nagle's algorithm

l    Fast retransmit

l    Congestion avoidance

l    Packet retransmission upon error/lost/out of order packet reception

l    Client or server mode

Ø    Configurable TX and RX replay buffer per session:

l  Embedded FPGA memory

l  4KB to 64KB per session

l External memory

l DDR4, DDR3, RLDRAM, SSRAM, et al.

l  4KB to 512MB per session

l    Protection Against Wrapper Sequences (PAWS)

l    Configurable port number

l    IPv4 with future upgrade paths to IPv6/IPng

Ø    TBD (consult factory)

l    Configurable timeouts

l    Targeted and tested in both Xilinx and Intel/Altera FPGAs

Ø    Xilinx UltraScale, UltraScale+

Ø    Intel/Altera Arria-10/Stratix-10

l    64-bit bus interface to MAC:

Ø    Synchronous FIFO clocked at 156.25Mhz

Ø    Optional asynchronous FIFO interface with 4-6 clocks cycles of added latency

Ø    128/256-bit on roadmap for 40/100 GbE.


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