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Xilinx Zynq® UltraScale+™ FMC PlatformPlatform

Xilinx Zynq® UltraScale+™ FMC PlatformPlatform

产品型号 : HTG-Z999

2018-06-25 浏览次数: 306
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Supported by Xilinx Zynq UltraScale+ ZU6EG, 9EG, or 15EG FPGA, multiple expansion ports and its unique architecture, the HTG-Z999 can be used as daughter card adding processing capability and/or FPGA gate density to Vita57.1 or 57.4 compliant FPGA carrier boards or as standalone host module.


Modular architecture of the HTG-Z999 ZYNQ UltraScale+ platform provides great level of versatility through two (one male and one female) industry standard Vita57.1 FPGA Mezzanine Connectors (FMC) and one  HTG High-Speed Bus using Samtec Z-Ray interposer. The male FMC connector (installed on the back side) mates with Vita57.1 or 57.4 FPGA carrier boards through singled ended and/or  GTH serial I/Os to provide processing power and additional FPGA density to designs. The female FMC connector (installed on the front side) provides access to the ARM processor's singled ended and GTR serial I/Os. The HTG High-speed ZRAY Bus provides access to 12 GTH Serial Transceivers of the FPGA (PL), single-ended I/O pins (for control functions) and adjustable power supplies for interfacing with daughter cards  such as Hybrid Memory Cube (HMC), QSFP+, SFP+, FireFly, and CXP.


► Xilinx Zynq UltraScale+ ZU6EG, 9EG, or 15EG FPGA in B1156 package
► x2 Vita57.1 FPGA Mezzanine Connectors (FMC) 
    - Male connector mating with FPGA carrier boards (daughter card mode)
    - Female connector with processor's I/Os mating with FMC daughter cards (carrier card mode)
► High-Speed / High-Performance Z-RAY interface with 12 GTH Serial Transceivers, control I/Os, and 12.V and 3.3V  power pins 
   - Available Modules: 
      Hybrid Memory Cube (HMC), SFP+, QSFP+, CXP, and Samtec FireFly
► DDR4 Components (x10)
      - 2.5GB for the processor side
      - 2.5GB for the programmable logic
► Configuration Flash
► ARM Debug port
► USB/UART
► Programmable Clocks (with default frequencies but programmable through I2C bus)
► XADC Headers
► JTAG Header
► Size: 5.5" x 2.7" (140mm x 69mm)


Front View with FMC female connector (hosting daughter cards) 

Back View with FMC male connector (interfacing with other FPGA carrier boards) and Z-Ray port

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